1. Technical Field
The present invention disclosed herein relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio.
2. Description of the Related Art
A semiconductor device includes transistors integrated on a semiconductor substrate. In a conventional semiconductor device, the transistors are disposed on a semiconductor wafer two-dimensionally. When the transistors are two-dimensionally arranged, the degree of integration in the semiconductor device is determined by the size of the minimum line width, which is formed during a patterning process. However, since very expensive optical equipment is required to form a delicate line width pattern, recently techniques in which transistors are arranged three-dimensionally have been suggested. Some semiconductor devices having three-dimensionally arranged transistors and methods of fabricating the same are disclosed by Samsung Electronics in Korean Patent Applications No. 2004-97003, No. 2005-16608, and No. 2006-12712. Specifically, since the transistors are fabricated on a semiconductor such as silicon, forming of an additional semiconductor layer on a semiconductor wafer is required to form transistors three-dimensionally. According to the Korean Patent Application No. 2004-97003, the additional semiconductor layer may be formed using an epitaxial technique that uses the semiconductor wafer as a seed layer.
On the other hand, according to the three-dimensionally arranged transistors, the degree of integration in the semiconductor device may increase, but the line formation for accessing each of the transistors becomes more difficult compared to a semiconductor device having two-dimensionally arranged transistors. In more detail, as disclosed in the Korean Patent Application No. 2004-97003, a lower circuit is formed on a semiconductor wafer; at least one semiconductor layer is formed on the lower circuit by using an epitaxial process; an upper circuit is formed on the semiconductor layer; and lines (e.g., bit lines or source lines) that are connected to the lower and/or upper circuits are formed on the upper circuit. Consequently, the distance between the line and the semiconductor wafer is drastically increased in the case of a semiconductor device with three-dimensionally arranged transistors. This distance determines the depth required of a contact hole, which is formed below the lines. Methods of fabricating conventional contact holes will be described below with reference to FIGS. 1A and 1B, but those methods are inappropriate for forming the contact holes having the increased depth in a desirable shape for three-dimensionally arranged transistors.
FIGS. 1A and 1B are cross-sectional views of a manufacturing process illustrating a method of forming a conventional contact hole.
Referring to FIG. 1A, transistors (not shown) that constitute a lower circuit are formed on a semiconductor wafer 10, and a lower interlayer insulating layer 20 is formed to cover the transistors. Next, the lower interlayer insulating layer 20 is patterned to form openings 25 that expose an upper surface of the semiconductor wafer 10, and then an epitaxial process is performed using the exposed semiconductor wafer 10 as a seed layer to form a semiconductor layer 30 that is disposed on the lower interlayer insulating layer 20 and fills the openings 25. An upper circuit (not shown) is formed on the semiconductor layer 30. An upper interlayer insulating layer 40 and a mask pattern 50 are sequentially formed on the resulting structure having the upper circuit.
Referring to FIG. 1B, the mask pattern 50 is used as an etching mask to sequentially pattern the upper interlayer insulating layer 40 and the semiconductor layer 30. Consequently, a contact hole 60 is formed in the upper interlayer insulating layer 40 and the semiconductor layer 30, and then a plug (not shown) is filled in the contact hole 60 to electrically connect a line with the semiconductor layer 30. As is well-known in the art, electric potentials of a gate electrode, source/drain electrodes and a substrate (i.e., well) need to be independently controlled for normally operating the transistors. Especially, for controlling the electric potential of the well, a well pick-up plug may be disposed between the semiconductor wafer 10 and the line.
On the other hand, although the semiconductor layer 30 is required to be formed with a thickness of several thousand angstroms, it has a relatively large electric resistance due to a low concentration of impurities. Accordingly, the well pick-up plug needs to be formed adjacent to the top surface of the semiconductor wafer 10 to reduce electric resistance between the well and the line. According to the technical requirements of the semiconductor device being manufactured, the forming of the contact hole 60 may include etching the semiconductor layer 30 with a depth of several thousand angstroms.
However, according to the conventional technique, the upper interlayer insulating layer 40 is formed of a silicon oxide layer, and the mask pattern 50 is formed of a silicon nitride layer that has an etch selectivity with respect to the upper interlayer insulating layer 40. In this case, since the mask pattern 50 (i.e., silicon nitride layer) does not have an etch selectivity with respect to the semiconductor layer 30 (i.e., silicon layer), the mask pattern 50 may be removed while etching the semiconductor layer 30, and thus the upper interlayer insulating layer 40 may be exposed. Consequently, as illustrated in FIGS. 1B, 2A, and 2B, the upper portion of the contact hole 50 widens and this causes technical difficulties and product defects during subsequent processes. The present invention addresses these and other disadvantages of the conventional art.